Generally, IC devices have different layers to define the component layout and wire connections between the components in the device. In the manufacture of IC devices, circuit components (such as transistors, capacitors, and diodes) are placed on layers that are separate from the layers that contain the wire connections. Routing is the process of adding wires to connect all the placed circuit components under certain design constraints. The layers where routing takes place are typically known as routing layers.
The routing information in an IC design has great impact on interconnect length, and thus the power consumption of the device. In portions of many designs, the routing demand can be close to the available resources; these regions are deemed congested or blocked. In the design flow of an IC device, routing is performed during compilation in a step called place-and-route.
The layers in an IC device are formed using masks that have been either pre-engineered or custom-designed. The customization of masks typically requires long design cycles and substantial non-recurrent engineering (NRE) costs. Some IC devices such as custom application-specific integrated circuits (ASICS) and semi-custom ASICs are designed using customized masks. At the other end of the spectrum, some IC devices such as field-programmable gate arrays FPGAs are designed without customized masks. For certain purposes, it is sometimes desirable to build a maskless device prototype and convert the prototype to a device for mass production when the design is finalized. The converted design will perform the same functionalities as the design it was converted from; in other words, both designs are functionally equivalent. Such a conversion greatly reduces NRE and mask costs, and shortens the development cycle. An example of such a conversion involves converting the design of an FPGA prototype to the design of a structured ASIC device.
The conversion of a first IC design to a functionally equivalent second IC design typically involves performing separate compilations on both designs. However, the quest for ever shorter development cycles has led some electronic design automation (EDA) software to provide early information required fora user to predict whether the compilation of the second IC design will be successful. Current EDA software provides early identification on the usage of resources such as logic usage, memory requirements, and I/O specification. Resource usage information is a good indication of how feasible it is to convert a first IC design to a second IC design. However, the early resource usage information provided by current EDA software does not give an accurate indication of the routability of the second IC design after it has been converted from a first IC design. Conversions that are predicted to be successful might encounter routing problems during the actual compilation of the second IC design due to the different routing architecture for both IC devices. Therefore, it is pertinent that early information on the routability of a design is made available for a user to accurately predict the outcome of the conversion.